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w921e840a/W921C840 4-bit microcontroller publication release date: july 1999 - 1 - revision a3 table of contents- 1. general description ........................................................................................................ .................3 2. features................................................................................................................... ..............................3 3. pin configurations......................................................................................................... ....................6 40-pin dip..................................................................................................................... .............................6 48-pin qfp..................................................................................................................... ............................7 4. pin description............................................................................................................ .........................9 5. block diagram .............................................................................................................. ......................10 6. functional description ..................................................................................................... ............11 6.1 rom memory map ............................................................................................................ ...............11 6.2 ram memory map............................................................................................................ ................12 6.2.1 special control register area .................................................................................................12 6.2.2 stack register area ................................................................................................................14 6.2.3 working register area ............................................................................................................15 6.3 internal oscillator circuit ............................................................................................... ....................15 6.4 initial state ............................................................................................................. ...........................16 6.5 input/output ............................................................................................................................... .......17 6.5.1 normal/special function selection of i/o ................................................................................ 17 6.5.2 pull high and open drain control of i/o .................................................................................19 6.6 serial port ............................................................................................................... ..........................21 6.7 dtmf generator............................................................................................................ ...................24 6.8 beep tone generator ....................................................................................................... ................25 6.9 d/a converter ............................................................................................................. ......................26 6.10 comparator............................................................................................................... ......................27 6.11 timer/counter ............................................................................................................ .....................28 6.11.1 tm0 ............................................................................................................................... .......28 6.11.2 tm1 ............................................................................................................................... .......30 6.11.3 tm2 ............................................................................................................................... .......32 6.11.4 tm3 ............................................................................................................................... .......34 6.11.5 arbitrary waveform generator ........................................................................................... ...35
w921e840a/W921C840 - 2 - 6.12 interrupt................................................................................................................ ...........................35 6.12.1 interrupt control register ......................................................................................................35 6.12.2 interrupt enable flag ............................................................................................................36 6.13 operating mode ........................................................................................................... ...................37 6.13.1 normal mode ........................................................................................................................37 6.13.2 hold mode ............................................................................................................................37 6.13.3 stop mode ............................................................................................................................39 6.14 initial condition register of eprom program method ....................................................................41 6.15 reset .................................................................................................................... ..........................41 6.15.1 reset by reset ...................................................................................................................41 6.15.2 reset by watch dog timer ...................................................................................................41 7. absolution maximum ratings ................................................................................................. ......42 8. electrical characteristics................................................................................................. ........42 8.1 dc characteristics ........................................................................................................ ....................42 8.2 ac characteristics ........................................................................................................ ....................45 9. addressing mode ............................................................................................................ ..................47 9.1 rom addressing mode....................................................................................................... ..............47 9.1.1 indirect call addressing mode: (1 word/2 cycles) ....................................................................47 9.1.2 long call/jump addressing mode: (2 words/2 cycles) .............................................................47 9.2 ram addressing mode ....................................................................................................... ..............47 9.2.1 direct addressing mode: (2 words/2 cycles) ............................................................................48 9.2.2 indirect addressing mode: (1 word/1 cycle) .............................................................................48 9.2.3 working register addressing mode: (1 word/1 cycle) ..............................................................48 9.3 look-up table addressing mode (1 word/2 cycles) ..........................................................................4 8 10. instruction code map ...................................................................................................... .............50 11. instruction set summary ................................................................................................... .........53 12. package dimensions........................................................................................................ ...............57 40-pin dip..................................................................................................................... ...........................57 48-pin qfp..................................................................................................................... ..........................57
w921e840a/W921C840 publication release date: july 1999 - 3 - revision a3 1. general description the w921e840a/W921C840 is single-chip cmos 4-bit microcontroller that is subset of w921e880a/w921c880. they features four multi-function timers, one channel dtmf generator, an 8-bit d/a converter circuit, ten interrupt sources, 48-level subroutine nesting, and built in four by one channel comparator circuit. two power down modes, hold and stop mode, reduce power dissipation. the excellent memory structure, 8k super eprom in w921e840a and 8k mask rom in W921C840 for program code and 512 x 4 bit ram minimize the need for external memory devices. the w921e840a/W921C840 are powerful microcontroller for wide range consuming applications, requiring few external components, which is especially suited for telecommunication design. 2. features operating voltage ? 2.8 to 5.5v operating voltage for w921e840a eprom type ? 2.4 to 5.5v operating voltage for W921C840 mask rom type operating frequency ? crystal or rc for main system clock ? crystal for 400 k, 800 k, 2 m, 3.58 m, 4 mhz ? rc up to 4 mhz memory ? 8k 10-bit rom (super eprom) ? 512 4-bit ram ? 64 4-bit special registers ? 16 4-bit working registers ? 128 4-bit general registers ? 304 4-bit multi-purpose registers stack ? 8-bit stack pointer i/o pins ? 20 bidirectional and individually controllable i/o lines ? p2 port: p2.0 to p2.3 large sink current pins and open drain option ? p3 port: p3.0 to p3.3 multi-function i/o ? p4 port: p4.0 to p4.3 open drain and pull high resistor option, multi-function i/o ? p5 port: p5.0 to p5.3 multi-function i/o ? p6 port: p6.0 to p6.3 open drain and pull high resistor option, multi-function i/o ? 14 bidirectional i/o lines ? pa port: pa.0 to pa.3 open drain and pull high resistor option
w921e840a/W921C840 - 4 - ? pb port: pb.0 to pb.3 open drain and pull high resistor option ? pc port: pc.1 to pc.3 open drain and pull high resistor option ? pd port: pd.0 to pd.1 open drain and pull high resistor option serial i/o interface ? clock synchronous multi-nibbles serial transmitter/receiver interface dtmf generator ? one channel dtmf generator beep tone generator ? one channel beep tone generator 8-bit d/a converter ? one channel 8-bit d/a converter voltage comparator ? multiplexed four channel voltage comparator timer/counter ? timer 0: 2 to 19 order divider auto-reload timer watch-dog timer ? timer 1: 2 to 19 order divider auto-reload timer arbitrary waveform generator external event counter ? timer 2: 2 to 19 order divider auto-reload timer arbitrary waveform generator period/pulse width measurement function ? timer 3: 2 to 19 order divider auto-reload timer interrupt ? four external sources: int0 (p4.3), p4 port (p4.0 to p4.2) ? six internal sources: timer 0, timer 1, timer 2, timer 3, comparator, serial port operating mode (system clock) ? normal mode: system clock operating ? hold mode: no operation except for oscillator (system clock stops only) ? stop mode: no operation including oscillator
w921e840a/W921C840 publication release date: july 1999 - 5 - revision a3 addressing mode ? rom: indirect call addressing mode long jump/call addressing mode ? ram: direct addressing mode indirect addressing mode working register addressing mode ? look-up table addressing mode instruction sets ? 117 instruction sets package type ? 40-pin dip, 48-pin qfp the w921e840a/W921C840 microcontroller series are shown in the following table: part no. package type function w921e840a/ W921C840 40-pin dip with pin pd.0, pd.1, btg without dual clock xt , xt, pc.0 w921e841a/ w921c841 40-pin dip with dual clock xt , xt, pc.0 without pin pd.0, pd.1, btg w921e842a/ w921c842 40-pin dip with pin pd.0, pd.1, pc.0 without dual clock xt , xt, btg w921e843a/ w921c843 40-pin dip with dual clock xt , xt, btg without pin pd.0, pd.1, pc.0 w921e844a/ w921c844 48-pin qfp with pin pd.0, pd.1, pc.0, btg, dual clock xt , xt
w921e840a/W921C840 - 6 - 3. pin configurations 40-pin dip w921e840a - 843a /W921C840 - 843 1 21 pin name dip40 pin name dip40 p2.0 1 p6.3/rclk 21 p2.1 2 pa.0 22 p2.2 3 pa.1 23 p2.3 4 pa.2 24 p3.0/ani0 5 pa.3 25 p3.1/ani1 6 pb.0 26 p3.2/ani2 7 pb.1 27 p3.3/ani3 8 pb.2 28 p4.0 9 pb.3 29 p4.1 10 pc.0 or btg 30 p4.2 11 pc.1 31 p4.3/int0 12 pc.2 32 p5.0/tm1 13 pc.3 33 p5.1/tm2 14 dtmf 34 p5.2/v ref 15 pd.0 or xt 35 p5.3/daout 16 pd.1 or xt 36 p6.0/wdata 17 reset 37 p6.1/wclk 18 osco 38 p6.2/rdata 19 osci 39 v ss 20 v dd 40
w921e840a/W921C840 publication release date: july 1999 - 7 - revision a3 3. pin configurations, continued 48-pin qfp w921e844a / w921c844 nc p3.1/ani1 p3.2/ani2 p3.3/ani3 p4.0 p4.1 p4.2 p4.3/int0 p5.0/tm1 p5.1/tm2 p5.2/vref nc n c p 5 . 3 / d a o u t p 6 . 0 / w d a t a p 6 . 1 / w c l k p 6 . 2 / r d a t a v s s p 6 . 3 / r c l k p a . 0 p a . 1 p a . 2 p a . 3 n c pb.0 pb.1 pb.2 pb.3 btg pc.0 pc.1 pc.2 pc.3 dtm f pd.0 pd.1 n c x t / x t / r e s e t / o s c o o s c i v d d p 2 . 0 p 2 . 1 p 2 . 2 p 2 . 3 p 3 . 0 / a n i 0 1 48 36 37 12 13 24 25 2 3 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 22 23 26 27 28 29 30 31 32 33 34 35 38 39 40 41 42 43 44 45 46 47 pin name qfp 48 pin name qfp 48 nc 1 pb.0 25 p3.1/ani1 2 pb.1 26 p3.2/ani2 3 pb.2 27 p3.3/ani3 4 pb.3 28
w921e840a/W921C840 - 8 - continued pin name qfp 48 pin name qfp 48 p4.0 5 btg 29 p4.1 6 pc.0 30 p4.2 7 pc.1 31 p4.3/int0 8 pc.2 32 p5.0/tm1 9 pc.3 33 p5.1/tm2 10 dtmf 34 p5.2/v ref 11 pd.0 35 nc 12 pd.1 36 nc 13 nc 37 p5.3/daout 14 xt 38 p6.0/wdata 15 xt 39 p6.1/wclk 16 reset 40 p6.2/rdata 17 osco 41 v ss 18 osci 42 p6.3/rclk 19 v dd 43 pa.0 20 p2.0 44 pa.1 21 p2.1 45 pa.2 22 p2.2 46 pa.3 23 p2.3 47 nc 24 p3.0/ani0 48
w921e840a/W921C840 publication release date: july 1999 - 9 - revision a3 4. pin description symbol i/o function osci i main oscillator input pin with internal capacitor osco o main oscillator output pin p2.0 to p2.3 i/o ? i/o port 2 with large sink current p3.0/ani0 to p3.3/ani3 i/o i/o port 3 or analog input (ani0 to ani3) pins p4.0 i/o ? i/o pin p4.0 or the input pin of interrupt port p4.1 i/o ? i/o pin p4.1 or the input pin of interrupt port p4.2 i/o ? i/o pin p4.2 or the input pin of interrupt port p4.3/int0 i/o ? i/o pin p4.3 or int0 input pin p5.0/tm1 i/o i/o pin p5.0 or the controlled pin of timer 1 p5.1/tm2 i/o i/o pin p5.1 or the controlled pin of timer 2 p5.2/v ref i/o i/o pin p5.2 or the v ref input pin of the comparator p5.3/daout i/o i/o pin p5.3 or the output pin of 8-bit d/a converter p6.0/wdata i/o ? i/o pin p6.0 or the data output pin of serial interface p6.1/wclk i/o ? i/o pin p6.1 or the clock i/o pin of wdata p6.2/rdata i/o ? i/o pin p6.2 or the data input pin of serial interface p6.3/rclk i/o ? i/o pin p6.3 or the clock i/o pin of rdata pa.0 to pa.3 i/o ? i/o port a with wake up stop mode function pb.0 to pb.3 i/o ? i/o port b with wake up stop mode function pc.0 to pc.3 i/o ? i/o port c. pc.3 can be as 32.768 khz output buffer pd.0 or xt i/o ? i/o pin pd.0 or 32.768 khz subsystem clock output pin (with internal capacitor) pd.1 or xt i/o ? i/o pin pd.1 or 32.768 khz subsystem clock input pin dtmf o dual tone multi-frequency output pin btg o beep tone generator output pin reset i reset input pin with low active v dd i positive power supply input pin v ss i negative power supply input pin notes: ? open drain option by software ? open drain and pull high resistor option by software
w921e840a/W921C840 - 10 - 5. block diagram port p2 p2.0-p2.3 port p3 p3.0-p3.3 port p4 p4.0-p4.3 port p5 p5.0-p5.3 port p6 p6.0-p6.3 port pa pa.0-pa.3 port pb pb.0-pb.3 port pc pc.0-pc.3 a reg. b reg. alu ram 512 x 4 timer 0 dtmf generator dtmf stack pointer port pd pd.0-pd.1 osci osco oscillator and system control prescaler timer 1 timer 2 timer 3 w reg. u reg. co-u reg. program counter eprom 8k x 10 decoder and control circuit v reg. co-v reg. + - p5.3/daout (ani0 to ani3) mux mux p5.2/v or ref d/a convertor d/a msb d/a lsb reset v dd v ss xt xt beep tone generator btg port mode register
w921e840a/W921C840 publication release date: july 1999 - 11 - revision a3 6. functional description 6.1 rom memory map interrupt area 0000h 000fh 0010h 1fffh indirect call and look-up table area long call/jump area 0fffh 1000h 8192 x 10-bit 0000h jmpl instruction (reset) 0001h xxxxx xxxxx 0002h jmpl instruction (int0) 0003h xxxxx xxxxx 0004h jmpl instruction (tm0) 0005h xxxxx xxxxx 0006h jmpl instruction (tm1) 0007h xxxxx xxxxx 0008h jmpl instruction (tm2) 0009h xxxxx xxxxx 000ah jmpl instruction (comparator / tm3) 000bh xxxxx xxxxx 000ch jmpl instruction (p4.0 to p4.2) 000dh xxxxx xxxxx 000eh jmpl instruction (serial port) 000fh xxxxx xxxxx priority: reset > int0 > tm0 > tm1 > tm2 > (comparator / tm3) > p4.0 to 4.2 > serial port
w921e840a/W921C840 - 12 - 6.2 ram memory map 000h speical control registers serial buffer registers stack registers or general registers general registers 03fh 040h 04fh 050h 07fh 080h 0ffh 100h 17fh 180h 1ffh 000 063 064 079 080 127 128 255 256 383 384 511 working registers general registers serial buffer registers or (040h to 0ffh) (050h to 14eh) general registers serial buffer registers stack registers (040h to 1ffh) (512 x 4-bit) 6.2.1 special control register area there are 64 4-bit registers in the special control register area. all control registers such as dtmf control register, serial speed control register, ..., etc. are in this area. please refer to the following table for detailed register map. addr. description abbreviation initial value 000h reserved or system clock control register (sysccr) 00h 001h reserved - - 002h reserved - - 003h port p4 pull high resistor register (p4ph) 00h 004h port p4 output type register (p4tp) 00h 005h port p6 pull high resistor register (p6ph) 00h 006h port p6 output type register (p6tp) 00h 007h port pabcd pull high resistor register (pabcdph) 00h 008h port pabcd output type register (pabcdtp) 00h 009h serial lsb nibble register (srlnr) 02h
w921e840a/W921C840 publication release date: july 1999 - 13 - revision a3 6.2.1 special control register map, continued addr. description abbreviation initial value 00ah serial msb nibble register (srmnr) 00h 00bh serial speed control register (srspc) 00h 00ch serial clock inverter control register (srinv) 00h 00dh port p2 output type register (p2tp) 00h 00eh reserved - 00fh port p3 i/o status control register ( p3io ) 00h 010h port p4 i/o status control register ( p4io ) 00h 011h port p5 i/o status control register ( p5io ) 00h 012h port p6 i/o status control register ( p6io ) 00h 013h dtmf oscillation control register (oscctr) 00h 014h dtmf register (dtmf) 00h 015h row/column frequency control register (rcctl) 00h 016h d/a control register (dactl) 00h 017h d/a converter lsb data register (dalsb) 00h 018h d/a converter msb data register (damsb) 00h 019h com parator analog input multiplexer (animux) 00h 01ah comparator control register (comptr) 04h 01bh reserved - 01ch tm1 read only msb data register (tm1rm) 0fh 01dh tm1 read only lsb data register (tm1rl) 0fh 01eh tm2 read only msb data register (tm2rm) 0fh 01fh tm2 read only lsb data register (tm2lm) 0fh 020h tm0 control register (tm0cr) 00h 021h tm0 msb data register (tm0msb) 0fh 022h tm0 lsb data register (tm0lsb) 0fh 023h tm0 status register (sttm0) 00h 024h reserved or timer 0 low speed register (tm0lsr) 00h 025h tm1 control register (tm1cr) 00h 026h tm1 msb data register (tm1msb) 0fh 027h tm1 lsb data register (tm1lsb) 0fh 028h tm1 status register (sttm1) 00h 029h tm1 trigger condition register ( tgtm1) 00h 02ah tm2 control register (tm2cr) 00h 02bh tm2 msb data register (tm2msb) 0fh
w921e840a/W921C840 - 14 - 6.2.1 special control register map, continued addr. description abbreviation initial value 02ch tm2 lsb data register (tm2lsb) 0fh 02dh tm2 status register (sttm2) 00h 02eh tm2 trigger condition register (tgtm2) 00h 02fh tm3 control register (tm3cr) 00h 030h tm3 msb data register (tm3msb) 0fh 031h tm3 lsb data register (tm3lsb) 0fh 032h tm3 status register (sttm3) 00h 033h reserved - 034h interrupt enable flag (enint) 00h 035h stop mode released flag (stprf) 08h 036h hold mode released flag 1 (hmrf1) 00h 037h hold mode released flag 2 (hmrf2) 00h 038h hold mode released flag 3 (hmrf3) 00h 039h interrupt control register 1 (intct1) 00h 03ah interrupt control register 2 (intct2) 00h 03bh interrupt control register 3 (intct3) 00h 03ch hold released status flag 1 (hrsts1) 00h 03dh hold released status flag 2 (hrsts2) 00h 03eh hold released status flag 3 (hrsts3) 00h 03fh beep tone generator register (btgr) 00h 6.2.2 stack register area a 8-bit stack pointer indicates the stack located address from 040h to 0ffh. after power on reset the stack pointer will be set to 0ffh. the stack pointer will be decreased by 4 when the call/ callp or interrupt is accepted, and will be increased by 4 when the rtn or rtni instruction is executed. the format of the stack content is shown in the following table. 0ffh 0feh 0fdh 0fch 0fbh 0fah 0f9h 0f8h stack 0 stack 1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 zc pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 z c pc12 pc12
w921e840a/W921C840 publication release date: july 1999 - 15 - revision a3 6.2.3 working register area the located area from 040h to 04fh is known as working register. the instruction mov wrn, a or mov a, wrn can move the a accumulator data to the working register or move working register data to the a accumulator directly within the 1 word / 1 machine cycle. the other direct instructions such as mov mx, a or mov a, mx instruction are 2 words / 2 machine cycles. therefore the working register can save the program memory size in rom and improve the control speed in c application circuit. only the wr0 to wr7 are available in the arithmetic and logic operation (i. e. only 040h to 047h can be active). the instructions are as follows: add a, wrx adc a, wrx sub a, wrx sbc a, wrx anl a, wrx orl a, wrx xrl a, wrx cmp a, wrx where x = 0 to 7. 6.3 internal oscillator circuit there are dual clocks in this chip, one high speed, the other low speed. the block diagram is shown below: tm0 tm1 tm2 tm3 mux0 mux3 mux1 mux2 f tm0 f tm1 f tm2 f tm3 crystal type or rc type osci osco system clock (1/4) 11-bit prescaler f sys h f crystal type xt xt 1-bit scaler (1/2) 2-bit scaler (1/4) f osc l f mux0' 5-bit prescaler f sys0 f sys1 1 f 2 f sysccr.3 mask option sysccr.0 enable enable (sysccr.1) (sysccr.2) f sub
w921e840a/W921C840 - 16 - the detail function of the system clock control register (sysccr) is shown as below: sysccr register: (address = 000h, default data = 0h, only for w921e841a, 843a, 844a) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: f = f f = f f enable f enable f = f f disable f disable f = f tm0 sys0 tm0 sys1 osc 1 osc 2 h h l l the w921e840a/W921C840 provides a crystal or rc oscillation circuit selected by bit0 of ini register (refer to section 6.14) to generate the system clock through external connections. if a crystal oscillator is used, a crystal or ceramic resonator must be connected to osci and osco , and the capacitor is added optionally. the oscillator configuration is shown as follows. osci osco or osci osco rc type crystal type 6.4 initial state the w921e840a/W921C840 is reset either by a power-on reset or by using the external reset pin. the initial state of the w921e840a/W921C840 after the reset function is executed is described below. the evf interrupt request signal register value is random, so user must do clr evf, #11111111b instruction to clear all interrupt request signals after power-on reset. program counter (pc) 0000h stack pointer 0ffh special function registers refer to section 6.2.1 tm0, tm1, tm2, tm3 input clock fosc/8 tm0, tm1, tm2, tm3 contents 0ffh input/output input mode pm registers 1111b dtmf output disable (h-z) evf interrupt request signal register random
w921e840a/W921C840 publication release date: july 1999 - 17 - revision a3 6.5 input/output there are 34 i/o pins including 4 large sink current pins in this chip. all the i/o pins will remain in the input mode after power on reset. the i/o instructions are described as follows: mov a, px input port x to a accumulator mov b, px input port x to b accumulator mov px, a output a accumulator data to port x. mov px, b output b accumulator data to port x. the input or output status of port 2 to port 6 can be pin controlled by port mode register (pmx, where x = 2 to 6). data 0 of pmx indicates the corresponding pin as output mode, and data 1 indicates the relative pin as input mode. for example, mov pm2, #0101b, it sets p2.0 and p2.2 in input mode and p2.1 and p2.3 in output mode. the i/o instructions don't affect the i/o status in port 2 to port 6. the input or output mode of port a to port d only can be decided by i/o instructions. for example, mov a, px will change px to input mode and mov px, a will change it to output mode. 6.5.1 normal/special function selection of i/o some of the i/o ports can be programmed to special function via special control register. the detail functions are as follows: ? p2.0 to p2.3: four 15ma sink current normal i/o pins only ? p3.0 to p3.3: multi-function i/o pins (selected by p3io register) ? normal function i/o pins ? special function input pins p3io register: (address = 00fh, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: normal i/o p3.0 analog input pin 0 (ani0) normal i/o p3.1 normal i/o p3.2 normal i/o p3.3 analog input pin 1 (ani1) analog input pin 2 (ani2) analog input pin 3 (ani3)
w921e840a/W921C840 - 18 - ? p4.0 to p4.3: multi-function i/o pins (selected by p4io register) ? normal function i/o pins ? special function input pins p4io register: (address = 010h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: int0 normal i/o p4.0, interrupt disable interrupt port p4.0 interrupt port p4.1 interrupt port p4.2 normal i/o p4.3, interrupt disable normal i/o p4.2, interrupt disable normal i/o p4.1, interrupt disable ? p5.0 to p5.3: multi- function i/o pins (selected by p5io register) ? normal function i/o pins ? special function i/o pins p5io register: (address = 011h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: normal i/o p5.3 normal i/o p5.0 normal i/o p5.1 normal i/o p5.2 work as the timer 1 control pin work as the timer 2 control pin work as the vref input pin of the comparator work as the output pin of d/a converter (daout)
w921e840a/W921C840 publication release date: july 1999 - 19 - revision a3 ? p6.0 to p6.3: multi-function i/o pins (selected by p6io register) ? normal function i/o pins ? special function i/o pins p6io register: (address = 012h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: normal i/o p6.0 normal i/o p6.1 normal i/o p6.2 work as the data output pin of the wclk pin ( wdata ) work as the clock i/o pin of the wdata pin (wclk) work as the clock i/o pin of the rdata pin (rclk) 0: 1: work as the data input pin of the rclk pin ( rdata ) normal i/o p6.3 ? pa.0 to pa.3: normal function i/o pins only ? pb.0 to pb.3: normal function i/o pins only ? pc.1 to pc.3: normal function i/o pins only ? pd.0 to pd.1: normal function i/o pins only 6.5.2 pull high and open drain control of i/o some of the above i/o ports can be controlled with pull-high resistor or open drain by programming the special register. all pull- high resistors of the following descriptions are 400k ? under 3.0 voltage test condition. after power-on reset the following special register will all reset to 0h. ? p4.0 to p4.3: p4ph register: (address = 003h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: p4.0 without pull-high resistor p4.0 with pull-high resistor p4.1 without pull-high resistor p4.1 with pull-high resistor p4.2 without pull-high resistor p4.2 with pull-high resistor p4.3 without pull-high resistor p4.3 with pull-high resistor
w921e840a/W921C840 - 20 - p4tp register: (address = 004h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: p4.0 work as cmos type p4.0 work as open-drain type p4.1 work as cmos type p4.1 work as open-drain type p4.2 work as cmos type p4.2 work as open-drain type p4.3 work as cmos type p4.3 work as open-drain type ? p6.0 to p6.3 : p6ph register: (address = 005h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: p6.0 without pull-high resistor p6.0 with pull-high resistor p6.1 without pull-high resistor p6.1 with pull-high resistor p6.2 without pull-high resistor p6.2 with pull-high resistor p6.3 without pull-high resistor p6.3 with pull-high resistor p6tp register: (address = 006h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: p6.0 work as cmos type p6.0 work as open-drain type p6.1 work as cmos type p6.1 work as open-drain type p6.2 work as cmos type p6.2 work as open-drain type p6.3 work as cmos type p6.3 work as open-drain type
w921e840a/W921C840 publication release date: july 1999 - 21 - revision a3 ? pa, pb, pc, pd: pabcdph register: (address = 007h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: pa (4 pins) without pull-high resistor pa (4 pins) with pull-high resistor pb (4 pins) without pull-high resistor pb (4 pins) with pull-high resistor pc (3 pins) without pull-high resistor pc (3 pins) with pull-high resistor pd (2 pins) without pull-high resistor pd (2 pins) with pull-high resistor pabcdtp register: (address = 008h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: 0: 1: 0: 1: pa (4 pins) work as cmos type pa (4 pins) work as open-drain type pb (4 pins) work as cmos type pb (4 pins) work as open-drain type pc (3 pins) work as cmos type pc (3 pins) work as open-drain type pd (2 pins) work as cmos type pd (2 pins) work as open-drain type ? p2: p2tp register: (address = 00dh, default data = 0h) b3 b2 b1 b0 0: 1: p2 (4 pins) work as cmos type p2 (4 pins) work as open-drain type reserved reserved 0: 1: pc.3 works as normal i/o port (cmos type) pc.3 works as 32.768khz output buffer (open-drain type) only for w921e841a, 843a, 844a 6.6 serial port the w921e840a/W921C840 has a clock-synchronous serial interface which transmits and receives 8-bit data as default. user can program the p6io register to select port p6 as the serial port. the serial transmitter/receiver function can be operated with multi-nibble function and the lsb of every nibble is transmitted/received first. the serial transmitted/received data are come from or are stored into the serial buffer registers (address 050h to 14eh); how many nibbles will be transmitted/received is decided by the serial msb nibble register (srmnr, address = 00ah) and serial lsb nibble register (srlnr, address = 009h).
w921e840a/W921C840 - 22 - srmnr register: (address = 00ah, default data = 0h) b3 b2 b1 b0 srlnr register: (address = 009h, default data = 2h) b3 b2 b1 b0 the default data in srmnr and srlnr are 0 and 2, meaning that the default serial interface is used to transmit/receive 8-bit data serially. as soon as the above two register are programmed and the instructions such as sop or sip are executed, the serial transmitter/receiver multi-nibble function will be performed. the transmitted/received number will be auto increased by one when each nibble is transmitted/received until the number is equal to srlnr, srmnr registers. even if the hold instruction is executed, the sop or sip function will continue executing until the transmitter/receiver function has been completed. however, executing the stop instruction will stop all serial transmitter/receiver function. the transceiver data will be latched on the rising or falling edge of the clock; this is determined by the serial clock inverter control register (srinv, address = 00ch). before sop or sip instruction is executed the srinv register must be set to the exact value. once the bit3 and bit2 of srinv register are both cleared to zero, the serial transceiver function will be reset to initial status immediately. srinv register: (address = 00ch, default data = 0h) b3 b2 b1 b0 0: serial data latch at sclk1/sclk2 rising edge (normal high) 1: serial data latch at sclk1/sclk2 falling edge (normal low) 1: sclk1 and sdata1 enable 1: sclk2 and sdata2 enable 0: sclk1and sclk2 pins work as the internal clock output pin 1: sclk1and sclk2 pins work as the external clock input pin 0: sclk2 and sdata2 disable (h-z) 0: sclk1 and sdata1 disable (h-z)
w921e840a/W921C840 publication release date: july 1999 - 23 - revision a3 the serial interface configuration is shown below: p6io.2 p6io.1 p6io.0 srinv.2 srinv.3 sdata sclk serial buffer registers 050h 14eh wdata wclk rdata rclk p6.0 p6.1 p6.2 p6.3 to port p6 normal i/o register p6io.3 to port p6 system clock 1/4 serial clock speed control circuit f sys serial/parallel i/o buffer clock source and latch control circuit vdd port p6 pull-high resisters p6ph high speed clock the internal serial clock can be controlled by the serial clock speed control register (srspc); the format is as follows: srspc register: (address = 00bh, default data = 0h) b3 b2 b1 b0 b1 b0 input frequency 00 01 10 11 fsys/4 hz fsys/8 hz fsys/16 hz b3 b2 00 00 00 00 01 01 01 01 10 00 01 10 11 1 1 0 0 00 01 10 fsys/32 hz fsys/64 hz fsys/128 hz fsys/256 hz fsys/512 hz fsys/1024 hz fsys/2048 hz reserved
w921e840a/W921C840 - 24 - normally the wclk or rclk pin will remain in high state and the serial data will be latched at the rising edge of the wclk or rclk signal, but the serial clock inverter control register (srinv) will invert the above function. in this case wclk or rclk pin will remain in low state and the serial data will be latched at the falling edge of the wclk or rclk signal. the transmitting serial clock can come from wclk or rclk, depending on which one is enable. if the serial function is disabled, it will cause the relative pins to be high impendance and it will not affect the contents of serial buffer registers (start at address 050h). 6.7 dtmf generator there is one dual tone multi-frequency (dtmf) generator channel in this chip. the correct dtmf output frequency is decided by the oscctr register as shown below: oscctr register: (address = 013h, default data = 0h) b3 b2 b1 b0 reserved b2 b1 b0 000 001 010 011 100 101 osc. selection 400 khz 800 khz 2 mhz 4 mhz reserved 3.58mhz there are four bits in the dtmf register; the functions are described in the following table: dtmf register: (address = 014h, default data = 0h) b3 b2 b1 b0 function description x x 0 0 column 1 (1209 hz) output x x 0 1 column 2 (1336 hz) output x x 1 0 column 3 (1477 hz) output x x 1 1 column 4 (1633 hz) output 0 0 x x row 1 (697 hz) output 0 1 x x row 2 (770 hz) output 1 0 x x row 3 (852 hz) output 1 1 x x row 4 (941 hz) output note: x ? don't care
w921e840a/W921C840 publication release date: july 1999 - 25 - revision a3 the output frequency of the row and column will be controlled by the row/column frequency control register (rcctl). rcctl register: (address = 015h, default data = 0h) b3 b2 b1 b0 0: 1: 0: 1: row frequency disable row frequency enable column frequency disable column frequency enable 0: 1: dtmf disable (h-z) dtmf enable reserved the following table shows the dtmf keypad and its frequency. 1 4 7 * 2 5 8 0 3 6 9 # r1 r2 r3 r4 c1 c2 c3 key frequency r1 r2 r3 r4 c1 c2 c3 697 hz 770 hz 852 hz 941 hz 1209 hz 1336 hz 1477 hz a b c d c4 c4 1633 hz 6.8 beep tone generator there are four kinds of frequency that can output from the btg pin that works as beep tone generator. the btg pin can output the special frequency ? 2 khz, 1 khz, 630 hz or 520 hz, and the correct output frequency is decided by the oscctr register (address = 013h) and btgr register (address = 03fh) as shown below: btgr register: (address = 03fh, default data = 0h) b3 b2 b1 b0 reserved b1 b0 00 01 10 11 output freq. 2k hz 1k hz 630 hz 520 hz 0: disable beep tone generator (btg pin keep in high state) 1: enable beep tone generator if the beep tone generator is disabled by setting bit 3 of the btgr register to zero or after power on reset, the btg output pin will remain in high state.
w921e840a/W921C840 - 26 - 6.9 d/a converter the content of 8-bit d/a converter is divided into d/a msb data register (damsb) and d/a lsb data register (dalsb). the block diagram is shown below. damsb 4-bit register dalsb 4-bit register 8bit d/a converter ani0 ani1 ani2 ani3 animux register comptr.2 p5.2/vref p5.3/daout vneg vpos vani vref comptr.1 vrang = 1.5 v or (2/3)v dd comptr.3 dactl.2 ? d/a converter control register: dactl register: (address = 016h, default data = 0h) b3 b2 b1 b0 0: 1: d/a converter start d/a converter stop 1:vrang = 1.5v reserved reserved 0:vrang = (2/3)vdd when the dactl register bit0 is set by software, the 8-bit d/a converter starts converting. the only way to disable the d/a converter is to reset the bit0 of the dactl register using the software control. the analog signal will be output to the p5.3 pin in this chip if the i/o port works as the d/a output pin. the power source of the d/a converter can be selected from the (2/3)v dd or 1.5v by programming the dactl register bit2. ? d/a converter lsb data register dalsb register: (address = 017h, default data = 0h) b3 b2 b1 b0
w921e840a/W921C840 publication release date: july 1999 - 27 - revision a3 ? d/a converter msb data register damsb register: (address = 018h, default data = 0h) b3 b2 b1 b0 6.10 comparator there are 4-channel inputs to the comparator negative (can be programmed to positive) terminal, but only one channel will be active at a time. the control register is shown below. animux register: (address = 019h, default data = 0h) b3 b2 b1 b0 b0 b1 0 0 1 1 0 1 0 1 ani0 enable ani1 ani2 ani3 reserved reserved comptr register: (address = 01ah, default data = 4h) b3 b2 b1 b0 0: vpos voltage < vneg voltage 1: vpos voltage >= vneg volatge 0: compare stop 1: compare start (read only) 1: vref = p5.3/daout 0: vref = p5.2/vref 0: vneg = vref; vpos = vani 1: vneg = vani; vpos = vref when the comptr register bit0 is set by software, the comparator starts and the bit2 of the comptr register will be set to "1" initially. the comparing result will be stored in the bit2 of the comptr register and will keep this value until the bit0 of the comptr register is set again. the only way to disable the comparator is to reset the bit0 of the comptr register using the software control. the initial value of the comptr bit2 is "1", the falling edge of comptr bit2 will cause the comparator interrupt to become active if the enable flag of the comparator interrupt is set. the bit3 of the comptr register controls the source of input voltage reference (vref). the input reference voltage (vref) comes from external pin (p5.2/vref) or d/a converter analog signal output (p5.3/daout).
w921e840a/W921C840 - 28 - 6.11 timer/counter there are four timers (tm0, tm1, tm2 and tm3) in this chip, and all can be initialized at any time by writing data into the tm0, tm1, tm2 and tm3 set register. 6.11.1 tm0 tm0 can perform the following functions: 1. 2 to19 order divider 2. auto-reload timer 3. watch-dog timer tm0 control register tm0 interrupt logic watch dog timer tm0 control logic interrupt control register tm0 set register (8 bits) 8 order divider f tm0 f sys1 f sys0 tm0 low speed register system clock 1/4 f sys 11-bit prescaler 5-bit prescaler low speed clock 1/8 f sub high speed clock the format of the tm0 control register (tm0cr) is described below: tm0cr register: (address = 020h, default data = 0h) b3 b2 b1 b0 b1 b0 input frequency (f ) 00 01 10 11 fsys/2 hz fsys/256 hz fsys/1024 hz fsys/2048 hz reserved reserved sys0 the tm0 set register is divided into tm0 msb data register (tm0msb register, address = 021h, default = 0fh) and tm0 lsb data register (tm0lsb register, address = 022h, default = 0fh).
w921e840a/W921C840 publication release date: july 1999 - 29 - revision a3 tm0 will underflow when tm0 set register is from 00h to 0ffh and the value in the tm0msb and tm0lsb will be auto reloaded to the tm0 set register when the sttm0 bit2 is set. tm0 will decrease by 1 at the frequency of timer 0 clock after timer 0 has started. if at any time the sttm0 bit3 is from 0 to 1 (disable to enable) in the timer mode, the tm0msb and tm0lsb will be auto reloaded to the tm0 set register again and restart the timer 0. tm0 will stop operating while the sttm0 bit3 is reset to 0. the format of the tm0 low speed register (tm0lsr) is described below: tm0lsr register: (address = 024h, default data = 0h, only for w921e841a, 843a, 844a) b3 b2 b1 b0 b1 b0 input frequency (fsys1) 00 01 10 11 fsub/2 hz fsub/8 hz fsub/16 hz fsub/32 hz reserved reserved the tm0 starts to down count when the sttm0 register bit3 is set. when tm0 underflows, the sttm0 bit3 will be reset by hardware to stop tm0 if the auto-reload is disabled, but the sttm0 bit3 will not be reset if the auto-reload is enabled. when the tm0 normal function is performed, the watch-dog timer function will be disabled automatically. the format of the tm0 status register (sttm0) is described below: sttm0 register: (address = 023h, default data = 0h) b3 b2 b1 b0 0:tm0 stop 1:tm0 start 0:tm0 normal function selected 1:watch-dog timer (wdt) selected 0:wdt not underflow 1:wdt underflow 0:tm0 auto-reload disable 1:tm0 auto-reload enable if tm0 works as the watch-dog timer (wdt), the bit1 of the sttm0 register will be set when the wdt is underflow, in the meanwhile, the system is reset just as with power on reset except the sttm0 bit1. the wdt (sttm0 bit1) will be reset to zero only with the power on reset or the ram write mode. in the timer mode or event counter mode the time out will be the programming data subtract 1 ([tm0msb, tm0lsb]-1). it is the same in the tm1, tm2 and tm3.
w921e840a/W921C840 - 30 - 6.11.2 tm1 tm1 can perform the following functions: 1. 2 to19 order divider 2. auto-reload timer 3. arbitrary waveform generator 4. event counter tm1 interrupt logic interrupt control register tm1 set register (8 bits) 8 order divider system clock 1/4 11-bit prescaler tm1 read register tm1 control logic arbitrary waveform generator tm1 control register f tm1 f sys port 5.0 event counter logic 2 high speed clock the format of the tm1 control register (tm1cr) is described below: tm1cr register: (address = 025h, default data = 0h) b3 b2 b1 b0 b1 b0 input frequency (f ) 00 01 10 11 fsys/2 hz fsys/4 hz fsys/8 hz fsys/16 hz b3 b2 00 00 00 00 01 01 01 01 10 00 01 10 11 1 1 0 0 00 01 10 fsys/32 hz fsys/64 hz fsys/128 hz fsys/256 hz fsys/512 hz fsys/1024 hz fsys/2048 hz tm1 the tm1 set register is divided into tm1 msb data register (tm1msb register, address = 026h, default = 0fh) and tm1 lsb data register (tm1lsb register, address = 027h, default = 0fh).
w921e840a/W921C840 publication release date: july 1999 - 31 - revision a3 the tm1 read register is divided into tm1 read only msb data register (tm1rm register, address = 01ch, default = 0fh) and tm1 read only lsb data register (tm1rl register, address = 01dh, default = 0fh). the format of the tm1 status register (sttm1) is described below: sttm1 register: (address = 028h, default data = 0h) b3 b2 b1 b0 0:tm1 stop 1:tm1 start 0: 1: tm1 normal function selected special function selected reserved 0:tm1 auto-reload disable 1:tm1 auto-reload enable if the tm1 is in the timer mode, tm1 will underflow when it is from 00h to 0ffh and the value in the tm1msb and tm1lsb will be auto reloaded into the tm1 set register when the sttm1 bit2 is set. tm1 will decrease by 1 at the frequency of timer 1 clock after timer 1 has started. at any time the sttm1 bit3 is from 0 to 1 (disable to enable) the tm1msb and tm1lsb will be auto reloaded to the tm1 set register again and restart the tm1. tm1 will stop operating while the sttm1 bit3 is reset to 0. the tm1 starts to down count when the sttm1 register bit3 is set. when tm1 underflows, the sttm1 bit3 will be reset by hardware to stop tm1 if the auto-reload is disabled, but the sttm1 bit3 will not be reset if the auto-reload is enable. when the tm1 normal timer function is performed, the special function (event counter or arbitrary waveform generator) will be disabled automatically. the special function input or output is from or to p5.0 and the debounce time is one system clock ( f sys ). the format of the tm1 trigger/event counter condition register (tgtm1) is described below: tgtm1 register: (address = 029h, default data = 0h) b3 b2 b1 b0 0: event counter is falling edge trigger 1: event counter is rising edge trigger 0: special function work as event counter 1: special function work as arbitrary waveform generator 0: arbitrary waveform type 0 1: arbitrary waveform type 1 reserved
w921e840a/W921C840 - 32 - 6.11.3 tm2 tm2 can perform the following functions: 1. 2 to19 order divider 2. auto-reload timer 3. arbitrary waveform generator 4. period/pulse width measurement function period/pulse width measurement tm2 interrupt logic interrupt control register tm2 set register (8 bits) 8 order divider system clock 1/4 11-bit prescaler tm2 read register arbitrary waveform generator tm2 control register f tm2 f sys port 5.1 tm2 control logic high speed clock tm2cr register: (address = 02ah, default data = 0h) b3 b2 b1 b0 b1 b0 00 01 10 11 fsys/2 hz fsys/4 hz fsys/8 hz fsys/16 hz b3 b2 00 00 00 00 01 01 01 01 10 00 01 10 11 1 1 0 0 00 01 10 fsys/32 hz fsys/64 hz fsys/128 hz fsys/256 hz fsys/512 hz fsys/1024 hz fsys/2048 hz input frequency (f ) tm2 the tm2 set register is divided into tm2 msb data register (tm2msb register, address = 02bh, default = 0fh) and tm2 lsb data register (tm2lsb register, address = 02ch, default = 0fh). the tm2 read register is divided into tm2 read only msb data register (tm2rm register, address = 01eh, default = 0fh) and tm2 read only lsb data register (tm2rl register, address = 01fh, default = 0fh).
w921e840a/W921C840 publication release date: july 1999 - 33 - revision a3 the format of the status of tm2 register (sttm2) is described below: sttm2 register: (address = 02dh, default data = 0h) b3 b2 b1 b0 0: tm2 stop 1: tm2 start 0: tm2 normal function selected 1: special function selected 0: tm2 auto-reload disable 1: tm2 auto-reload enable reserved if the tm2 is in the timer mode, tm2 will underflow when it is from 00h to 0ffh and the value in the tm2msb and tm2lsb will be auto reloaded to the tm2 set register. tm2 will decrease by 1 at the frequency of timer 2 clock after timer 2 has started. if at any time the sttm2 bit3 is from 0 to 1 (disable to enable) the tm2msb and tm2lsb will be auto reloaded to the tm2 set register again and restart the tm2. tm2 will stop operating when the sttm2 bit3 is reset to 0 the tm2 starts to count when the sttm2 register bit3 is set. when tm2 underflows, the sttm2 bit3 will be reset by hardware to stop tm2 if the auto-reload is disabled, but the sttm2 bit3 will not be reset if the auto-reload is enabled. when the tm2 normal function is performed, the special function will be disabled automatically. the format of the tm2 trigger condition register (tgtm2) is shown below: tgtm2 register: (address = 02eh, default data = 0h) b3 b2 b1 b0 0: special function work as pulse/period width measurement 1: special function work as arbitrary waveform generator 0: arbitrary waveform type 0 1: arbitrary waveform type 1 b1 b0 00 01 10 11 trigger rising falling both in the pulse/period width measurement mode the measuring-data is the 1's complement of the exact data and the tm2 interrupt flag is set every 255 timer clock past or the 2nd trigger condition occurs. so the measured pulse/period width is (255(n 1) tm2) * t ?+ , n is the number of interrupt flag occurs, tm2 is the 1's complement of timer2 register, t is the period of timer 2 clock. the special function input or output is from or to p5.1.
w921e840a/W921C840 - 34 - 6.11.4 tm3 tm3 can perform the following functions: 1. 2 to19 order divider 2. auto-reload timer system clock 1/4 11-bit prescaler tm3 control register tm3 interrupt logic tm3 control logic interrupt control register tm3 set register (8 bits) 8 order divider f tm3 f sys high speed clock tm3cr register: (address = 02fh, default data = 0h) b3 b2 b1 b0 b1 b0 00 01 10 11 fsys/2 hz fsys/4 hz fsys/8 hz fsys/16 hz b3 b2 00 00 00 00 01 01 01 01 10 00 01 10 11 1 1 0 0 00 01 10 fsys/32 hz fsys/64 hz fsys/128 hz fsys/256 hz fsys/512 hz fsys/1024 hz fsys/2048 hz input frequency (f ) tm3 the tm3 set register is divided into tm3 msb data register (tm3msb register, address = 030h, default = 0fh) and tm3 lsb data register (tm3lsb register, address = 031h, default = 0fh). the format of the status of tm3 register (sttm3) is described below: sttm3 register: (address = 032h, default data = 0h) b3 b2 b1 b0 0: tm3 stop 1: tm3 start 0: tm3 auto-reload disable 1: tm3 auto-reload enable reserved reserved
w921e840a/W921C840 publication release date: july 1999 - 35 - revision a3 6.11.5 arbitrary waveform generator the tm1 and tm2 have the arbitrary waveform generator circuit. both have the same function as the following description. type 0: 256t nt nt t type 1: n = 0 will keep the waveform in the high state n = 1 will keep the waveform in the low state note: n is the value stored in the tm1 set reg. (tm1msb, tm1lsb) or tm2 set reg. (tm2msb, tm2lsb) 6.12 interrupt there are ten interrupt sources (four external and six internal sources) in the w921e840a/W921C840. all the pins of external sources?int0 (p4.3) and port p4 (p4.0 to p4.2)?are falling edge active. the priority of those interrupts is int0 > tm0 > tm1 > tm2 > ( comparator / tm3 ) > p4.0 to p4.2 > serial. 6.12.1 interrupt control register which interrupt is enabled is controlled by the interrupt control register1 to 3 (intct1 to intct3). the formats are shown below: intct1 register: (address = 039h, default data = 0h) b3 b2 b1 b0 0: tm0 interrupt disable 1: tm0 interrupt enable 0: tm1 interru p t disable 1: tm1 interrupt enable 0: tm2 interrupt disable 1: tm2 interrupt enable 0: tm3 interrupt disable 1: tm3 interrupt enable
w921e840a/W921C840 - 36 - intct2 register: (address = 03ah, default data = 0h) b3 b2 b1 b0 0: serial port interrupt disable 1: serial port interrupt enable 0: int0 pin interrupt disable 1: int0 pin interrupt enable 0: comparator interrupt disable 1: comparator interrupt enable reserved intct3 register: (address = 03bh, default data = 0h) b3 b2 b1 b0 0: pin p4.0 interrupt disable 1: pin p4.0 interrupt enable 0: pin p4.1 interrupt disable 1: pin p4.1 interrupt enable 0: pin p4.2 interrupt disable 1: pin p4.2 interrupt enable reserved 6.12.2 interrupt enable flag when the interrupt is enabled by the event, the program counter will jump to the interrupt address and the enable interrupt flag (enint) bit0 is cleared, at the same time, all the interrupt will be disabled. the only way to enable the interrupt again is to set the enint bit0 or execute the rtni instruction. enint register: (address = 034h, default data = 0h) b3 b2 b1 b0 0: disable all interrupt 1: enable all interrupt reserved reserved reserved when the interrupt is enabled by the event, the individual interrupt request signal is cleared by the hardware automatically, but the other interrupt request signals will remain the same condition. the only method of resetting the interrupt request signal is to execute the instruction clr evf, #i (i is a 8bits data, for example, clr evf, #00000001b instruction implies to clear tm0 interrupt request signal), it is a 2 words / 2 cycles instruction; the format of the immediate data is shown below. i3 i2 i1 i0 1: tm2 interrupt request signal is cleared 1: tm1 interrupt request signal is cleared 1: tm0 interrupt request signal is cleared 1: tm3 interrupt request signal is cleared i4 i5 i6 i7 1: serial port interrupt request signal is cleared 1: p4.0 to p4.2 interrupt request signal is cleared 1: int0 pin interrupt request signal is cleared 1: comparator interrupt request signal is cleared
w921e840a/W921C840 publication release date: july 1999 - 37 - revision a3 6.13 operating mode there are three types of operating mode in this chip ? normal mode, hold mode and stop mode. 6.13.1 normal mode all functions works well and the c operates according to the clock generated by the system clock. 6.13.2 hold mode in hold mode, all operations of c cease, except for the operation of the oscillator, timer/counter, serial port and interrupt active pins. the c enters hold mode when the hold instruction is executed. the hold mode can be released only by the reset pin or the interrupt request signal. before the device enters the hold mode, the hold mode release flag1, 2, 3 (hmrf1, 2, 3, address = 036h, 037h, 038h) must be set to define the hold mode release conditions. if interrupt condition is met and enabled in hold mode, the interrupt will be accepted to release hold mode and jump to interrupt vector to execute interrupt service routine. for more details, refer to the following flags and flow chart. hmrf1 register: (address = 036h, default data = 0h) 0 12345 6 0 1 2 3 4 5 6 7 8 9 a b c d e f l s b m s b 7 8 9 ab c de f 1w/1c 1w/2c 1w/3c 2w/2c 2w/3c 3w/3c undecided add a, #i adc a, #i sub a, #i sbc a, #i anl a, #i orl a, #i xrl a, #i cmp a, #i nop mov b, a mov mx, a mov @m, a mov w, a mov v, a mov u, a mov a, b mov mx, b mov @m, b mov a, mx mov b, mx mov a, @m mov a, w mov a, v mov a, u add a, mx adc a, mx sub a, mx sbc a, mx add a, @m adc a, @m sub a, @m sbc a, @m anl a, mx orl a, mx xrl a, mx cmp a, mx anl a, @m orl a, @m xrl a, @m cmp a, @m inc b dec b inc dp dec dp c lrb mx , b i t clrb @ m , bit s etb mx , b i t s etb @ m , b i t clr evf set cf mov b, @m srl a xch a, b sop sip rtn rtni hold stop srh a sll a slh a rrc a rlc a xch v, cv xch u, cu mov dp, #i xrl a, b cmp a, b clr cf hmrf2 register: (address = 037h, default data = 0h) b3 b2 b1 b0 0: serial port hold released disable 1: serial port hold released enable 0: int0 pin hold released disable 1: int0 pin hold released enable 0: comparator hold released disable 1: comparator hold released enable reserved hmrf3 register: (address = 038h, default data = 0h) b3 b2 b1 b0 0: pin p4.1 hold released disable 1: pin p4.1 hold released enable 0: pin p4.2 hold released disable 1: pin p4.2 hold released enable 0: pin p4.0 hold released disable 1: pin p4.0 hold released enable reserved
w921e840a/W921C840 - 38 - hold mode operation flow chart tm0 totm3; serial;comparator; falling change occurs at int0, p4.0 to p4.2 no yes no yes yes no yes no hold hmrfx hold release flag set? reset enint flag and individual request flag execute interrupt service routine intctx interrupt flag set? pc pc + 1 yes no interrupt enable? intctx interrupt flag set? yes no interrupt enable? in hold mode? reset enint flag and individual request flag execute interrupt service routine note: x is the corresponding flag bit of interrupt enable or hold mode release register
w921e840a/W921C840 publication release date: july 1999 - 39 - revision a3 the hold released status flag1, 2, 3 (hrsts1, 2, 3, address = 03ch, 03dh, 03eh) indicate by which interrupt source the hold mode has been released, and is loaded by hardware. when any bit of hrsts1, 2, 3 is "1," the hold mode will be released and hold instruction in invalid. the bit descriptions are as follows: hrsts1 register: (address = 03ch, read only, default data = 0h) b3 b2 b1 b0 1: hold was released by tm0 1: hold was released by tm1 1: hold was released by tm2 1: hold was released by tm3 hrsts2 register: (address = 03dh, read only, default data = 0h) b3 b2 b1 b0 1: hold was released by the int0 pin 1: hold was released by serial port 1: hold was released by comparator reserved hrsts3 register: (address = 03eh, read only, default data = 0h) b3 b2 b1 b0 1: hold was released by pin p4.0 1: hold was released by pin p4.1 1: hold was released by pin p4.2 reserved hrsts1, 2 and 3 are read only registers and can be reset by the instruction clr evf, #i. when evf has been reset, the corresponding bit of hrstsn (n = 1 to 3) is reset simultaneously. 6.13.3 stop mode the c enters the stop mode only when the stop instruction is executed. because the oscillator is stopped, all functions in this chip are stopped. the stop mode can be released by the reset pin, int0 pin, p4.0 to p4.2, pa port or pb port. the stop condition release flag (stprf, address = 035h) is the stop mode release control register.
w921e840a/W921C840 - 40 - stprf register: (address = 035h, default data = 8h) b3 b2 b1 b0 0: stop released by int0 (p4.3) is disable 1: stop released by int0 (p4.3) is enable 0: stop released by any pin of pb is disable 1: stop released by any pin of pb is enable 0: stop released by any pin of p4.0 to p4.2 is disable 1: stop released by any pin of p4.0 to p4.2 is enable 0: stop released by any pin of pa is disable 1: stop released by any pin of pa is enable when stop mode is active, if the stop condition release flag (stprf) is set before the stop instruction is executed, the low level signal on the p4, pa or pb ports will release the stop mode and a delay of 256 machine cycles occurs right after the stop mode is released, then the next instruction is executed or the program counter (pc) jumps to interrupt subroutine if the interrupt is enabled and interrupt request exists. the control flow chart is shown below: stop mode operation flow chart start stop enter stop mode int enable? yes no int vector rtni pc pc + 1 stop release no yes (only falling signal on int0 or p4.0 - p4.2) (pa, pb ports on low level state) system will delay 256 machine cycle automatically next instruction
w921e840a/W921C840 publication release date: july 1999 - 41 - revision a3 6.14 initial condition register of eprom program method there is one 4-bit of the initial condition register (not part of the ram) in w921e840a to control the micro-controller initial status after power-on. the format is described as following: ini register: (initial value = 0fh) b3 b2 b1 b0 0: osc acts as rc oscillator type 1: osc acts as crystal type reserved reserved f f 0: f1 = f , f2 = f h l 1: f1 = f , f2 = f h l only for w921e841a, 843a, 844a 6.15 reset w921e840a/W921C840 provides two reset methods, pull low reset pin and watch dog timer reset. 6.15.1 reset by reset as reset pin is pulled low, system and all control registers are reset to initial state. after reset pin is in high level, system will delay 256 machine cycle time, then program is executed from address 000h. 6.15.2 reset by watch dog timer as watch dog timer underflows, the sttm0.1 is set, in the meantime, system and all control registers, except data 1 in sttm0.1 bit is reserved, are reset to initial state, then after a delay of 256 machine cycle time program is executed from address 000h. after system reset, user can detect sttm0.1 to recognize which method of reset was used before. 256 machine cycle reset all control reg. program executed from address 000h reset all control regs except sttm0.1. 256 machine cycle sttm0.1 program executed from address 000h
w921e840a/W921C840 - 42 - 7. absolution maximum ratings parameter symbol rating unit dc supply voltage v dd ? v ss -0.3 to +7.0 v v il v ss ? 0.3 input/output voltage v ih v dd + 0.3 v v ol v ss ? 0.3 v oh v dd + 0.3 power dissipation p d 120 mw operating temperature t opr 0 to +70 c storage temperature t stg -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 8. electrical characteristics 8.1 dc characteristics w921e840a eprom type (v dd ? v ss = 3.0v, f osc = 4.0 mhz, t a = 25 c, all outputs unloaded) parameter sym. conditions min. typ. max. unit operating voltage v dd ? 2.8 3.0 5.5 v operating current i op1 analog active, v dd = 5v, f osc = 4 mhz ? 9 12 ma i op2 analog disable, v dd = 5v, f osc = 4 mhz ? 5 7 ma operating current i op3 analog active, v dd = 3v, f osc = 800 khz ? 3.1 4.3 ma (active mode) i op4 analog disable, v dd = 3v, f osc = 800 khz ? 0.6 1.8 ma i op5 analog active, v dd = 3v, f osc = 400 khz ? 1.0 2.0 ma i op6 analog disable, v dd = 3v, f osc = 400 khz ? 0.4 1.2 ma i hm1 v dd = 5v, f osc = 4 mhz ? 1.2 3.5 ma hold mode current i hm2 v dd = 3v, f osc = 800 khz ? 0.3 0.7 ma i hm3 v dd = 3v, f osc = 400 khz ? 0.25 0.5 ma i hm4 v dd = 3v, f osc = 32.768 khz ? 50 80 a
w921e840a/W921C840 publication release date: july 1999 - 43 - revision a3 w921e840a eprom type dc characteristics, continued parameter sym. conditions min. typ. max. unit i sm1 v dd = 5v, f osc = 4 mhz ? 2.0 3.0 a stop mode current i sm2 v dd = 3v, f osc = 800 khz ? 1.0 3.0 a i sm3 v dd = 3v, f osc = 400 khz ? 1.0 3.0 a i sm4 v dd = 3v, f osc = 32.768 khz ? 1.0 3.0 a input high voltage v ih ? 0.7 v dd ? v dd v dd input low voltage v il ? 0 ? 0.3 v dd v dd pull-high resistor (p2, p4, p6, pa, pb, pc, pd) r ph v dd = 3v ? 400 ? k ? output high voltage v oh i oh = -0.5 ma v dd - 1.0 ? ? v output low voltage v ol1 i ol = 15 ma, port p2 ? ? 2.0 v ol2 i ol = 0.4 ma, other ports ? ? 0.4 v input leakage current v il v in = 0v, reset pin ? ? 1 a dtmf output dc level v tdc v dd = 2.8 to 5.5v 1.0 ? 3.0 v dtmf distortion thd v dd = 2.8 to 5.5v - -30 -23 db dtmf output voltage v to row group, rl = 5 k ? 130 150 170 mvrms pre-emphasis col/row 1 2 3 db d/a dc reference voltage v ref ? 0 ? 2/3 v dd d/a resolution voltage v rsl ? ? 1/256 ? v dac W921C840 mask rom type (v dd ? v ss = 3.0v, f osc = 4.0 mhz, t a = 25 c, all outputs unloaded) parameter sym. conditions min. typ. max. unit operating voltage v dd 4 mhz 2.4 - 5.5 v 2 mhz 2.0 - 5.5 v 400 khz 2.0 - 5.5 v operating current i op 4 mhz -- 1.0 -- ma (active mode) v dd = 3v 2 mhz -- 0.7 -- ma (analog all off) 400 khz -- 0.4 -- ma 4 mhz -- 2.5 -- ma v dd = 5v 2 mhz -- 2.2 -- ma 400 khz -- 1.5 -- ma
w921e840a/W921C840 - 44 - W921C840 mask rom type, continued parameter sym. conditions min. typ. max. unit hold mode current i hm1 v dd = 3v, f osc = 4 mhz -- 0.5 -- ma (analog all off) v dd = 5v, f osc = 4 mhz -- 2.0 -- ma hold mode current i hm2 v dd = 3v, f osc = 32.768 khz -- 10 -- a (analog all off) v dd = 5v, f osc = 32.768 khz -- 50 -- a stop mode current i sm v dd = 3v ? 1.0 3.0 a v dd = 5v ? 1.0 3.0 a input high voltage v ih ? 0.7 v dd ? v dd v dd input low voltage v il ? 0 ? 0.3 v dd v dd pull-high resistor (p2, p4, p6, pa, pb, pc, pd) r ph v dd = 3v ? 400 ? k ? output high voltage v oh i oh = -0.5 ma v dd ? 1.0 ? ? v output low voltage v ol1 i ol = 15 ma, port p2 ? ? 2.0 v ol2 i ol = 0.4 ma, other ports ? ? 0.4 v input leakage current v il v in = 0v, reset pin ? ? 1 a dtmf output dc level v tdc v dd = 2.8 to 5.5v 1.0 ? 3.0 v dtmf distortion thd v dd = 2.8 to 5.5v - -30 -23 db dtmf output voltage v to row group, rl = 5 k ? 130 150 170 mvrms pre-emphasis col/row v dd = 3.0 to 5.5v 1 2 3 db d/a dc reference voltage v ref ? 0 ? 2/3 v dd d/a resolution voltage v rsl ? ? 1/256 ? v dac
w921e840a/W921C840 publication release date: july 1999 - 45 - revision a3 8.2 ac characteristics w921e840a eprom type (v dd ? v ss = 3.0v, f osc = 4.0 mhz, t a = 25 c, all outputs unloaded) parameter sym. conditions min. typ. max. unit f osc1 ? 400 ? khz f osc2 ? 800 ? khz operating frequency f osc3 osci, osco ? 2 ? mhz f osc4 ? 3.58 ? mhz f osc5 ? 4 ? mhz operating sub-frequency f sub xt, xt ? 32.768 ? khz instruction cycle time t i one machine cycle ? 4/f osc ? s serial port data ready time t dr ? 200 ? ? ns serial port data hold time t dh ? 200 ? ? ns reset active width t raw ? 2 ? ? t i row 1 frequency (697hz) f row1 f osc = 4 mhz, 2mhz, 800 khz, 400 khz -0.5 ? +0.5 % f osc = 3.58 mhz -0.92 ? +0.92 row 2 frequency (770 hz) f row2 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 row 3 frequency (852 hz) f row3 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 row 4 frequency (941 hz) f row4 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 1 frequency (1209 hz) f col1 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 2 frequency (1336 hz) f col2 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 3 frequency (1477 hz) f col3 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 4 frequency (1633 hz) f col4 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 oscillator start time t ost osco ? 2 17 /f osc ? ms
w921e840a/W921C840 - 46 - W921C840 mask rom type (v dd ? v ss = 3.0v, f osc = 4.0 mhz, t a = 25 c, all outputs unloaded) parameter symbo l conditions min. typ. max. unit f osc1 ? 400 ? khz f osc2 ? 800 ? khz operating frequency f osc3 osci, osco ? 2 ? mhz f osc4 ? 3.58 ? mhz f osc5 ? 4 ? mhz operating sub-frequency f sub xt, xt ? 32.768 ? khz instruction cycle time t i one machine cycle ? 4/f osc ? s serial port data ready time t dr ? 200 ? ? ns serial port data hold time t dh ? 200 ? ? ns reset active width t raw ? 2 ? ? t i row 1 frequency (697hz) f row1 f osc = 4 mhz, 2 mhz, 800 khz, 400 khz -0.5 ? +0.5 % f osc = 3.58 mhz -0.92 ? +0.92 row 2 frequency (770 hz) f row2 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 row 3 frequency (852 hz) f row3 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 row 4 frequency (941 hz) f row4 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 1 frequency (1209 hz) f col1 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 2 frequency (1336 hz) f col2 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 3 frequency (1477 hz) f col3 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 col 4 frequency (1633 hz) f col4 same as row1 -0.5 ? +0.5 % -0.92 ? +0.92 oscillator start time t ost osco ? 2 17 /f osc ? ms
w921e840a/W921C840 publication release date: july 1999 - 47 - revision a3 9. addressing mode there are rom, ram, and look-up table addressing modes in this chip. 9.1 rom addressing mode there are two types of rom addressing mode in this chip: ? indirect call addressing mode (0000h to 0fffh) ? long call/jump addressing mode (0000h to 1fffh) 9.1.1 indirect call addressing mode: (1 word/2 cycles) b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code b3 b2 b1 b0 i3 i2 i1 i0 b register a register 0 i3 i2 i1 i0 b3 b2 b1 b0 a3 a2 a1 a0 rom code pc instruction: callp 9.1.2 long call/jump addressing mode: (2 words/2 cycles) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code rom code pc instruction: call, jmpl, jb0, jb1, jb2, jb3, jc, jnc, jz, jnz 9.2 ram addressing mode there are three types of ram addressing mode in this chip: ? direct addressing mode ? indirect addressing mode ? working register addressing mode
w921e840a/W921C840 - 48 - 9.2.1 direct addressing mode: (2 words/2 cycles) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code rom code ram address instruction: mov a, mx; mov b, mx; mov mx, a; mov mx, b; ..., etc. 9.2.2 indirect addressing mode: (1 word/1 cycle) b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 u register v register w register ram address instruction: mov a, @m; mov b, @m; mov @m, a; ..., etc. 9.2.3 working register addressing mode: (1 word/1 cycle) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 decoder code 0 0 0 1 0 0 m3 m2 m1 m0 rom code ram address instruction: mov a, wrn; mov wrn, a; ..., etc. 9.3 look-up table addressing mode (1 word/2 cycles) there is one special function look-up table addressing mode in this chip; the instruction is tbl i and the function is shown in the following table.
w921e840a/W921C840 publication release date: july 1999 - 49 - revision a3 b3 b2 b1 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 decoder code b3 b2 b1 b0 b11 b10 b9 b8 b12 0 rom address (0 to 4k) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 op2 op1 x y xy 00 01 10 11 op2 op1 disable disable b register a register port p2 both i3 to i0 b register a register rom code rom code rom code output to register or port a register disable example: . . . mov a, #03h mov b, #01h tbl 02h ; a = 0ch, b = port2 = 0dh . . . org 213h dc 3dch . . .
w921e840a/W921C840 - 50 - 10. instruction code map b9 = 0 b8 = 0 0 12345 6 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb msb 7 8 9 abc de f 1w/1c 1w/2c 1w/3c 2w/2c 2w/3c 3w/3c undecided add a, #i adc a, #i sub a, #i sbc a, #i anl a, #i orl a, #i xrl a, #i cmp a, #i nop mov b, a mov mx, a mov @m, a mov w, a mov v, a mov u, a mov a, b mov mx, b mov @m, b mov a, mx mov b, mx mov a, @m mov a, w mov a, v mov a, u add a, mx adc a, mx sub a, mx sbc a, mx add a, @m adc a, @m sub a, @m sbc a, @m anl a, mx orl a, mx xrl a, mx cmp a, mx anl a, @m orl a, @m xrl a, @m cmp a, @m inc b dec b inc dp dec dp clrb mx, bit clrb @m, bit setb mx, bit setb @m, bit clr evf set cf mov b, @m srl a xch a, b sop sip rtn rtni hold stop srh a sll a slh a rrc a rlc a xch v, cv xch u, cu mov dp, #i xrl a, b cmp a, b clr cf
w921e840a/W921C840 publication release date: july 1999 - 51 - revision a3 b9 = 1 b8 = 0 0123456 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb msb 7 89abcdef 1w/1c 1w/2c 1w/3c 2w/2c 2w/3c 3w/3c undecided jb0 jb2 jc jz jmpl jb1 jb3 jnc jnz call callp tbl mov pmx, #i
w921e840a/W921C840 - 52 - b9 = 1 b8 = 1 0123456 0 1 2 3 4 5 6 7 8 9 a b c d e f lsb msb 7 8 9 a b c d e f 1w/1c 1w/2c 1w/3c 2w/2c 2w/3c 3w/3c undecided mov a, #i mov b, #i mov mx, #i mov @m, #i mov a, wrn mov b, wrn mov wrn, a mov wrn, b mov a, px mov b, px mov px, a mov px, b add a, wrn adc a, wrn sub a, wrn sbc a, wrn anl a, wrn orl a, wrn xrl a, wrn cmp a, wrn
w921e840a/W921C840 publication release date: july 1999 - 53 - revision a3 11. instruction set summary machine code mnemonic function a b u v w status w/c memo arithmetic 00 0000 1010, xxxxxxxxxx add a, mx a + mx a a z, c 2/2 11 0100 0 i i i add a, wrx a + wrx a a z, c 1/1 x = 0 7 00 0000 1011 add a, @m a + @m a a u v w z, c 1/1 00 0001 1010, xxxxxx xxxx adc a, mx a + mx + c a a z, c 2/2 11 0100 1 i i i adc a, wrx a + wrx + c a a z, c 1/1 x = 0 7 00 0001 1011 adc a,@m a+ @m + c a a u v w z, c 1/1 00 0010 1010, xxxxxxxxxx sub a, mx a - mx a a z, c 2/2 11 0101 0 i i i sub a, wrx a - wrx a a z, c 1/1 x = 0 7 00 0010 1011 sub a, @m a - @m a a u v w z, c 1/1 00 0011 1010, xxxxxxxxxx sbc a, mx a - mx - c a a z, c 2/2 11 0101 1 i i i sbc a, wrx a - wrx - c a a z, c 1/1 x = 0 7 00 0011 1011 sbc a, @m a - @m - c a a u v w z, c 1/1 00 1000 i i i i add a, #i a + i a a z, c 1/1 00 1001 i i i i adc a, #i a + i +c a a z. c 1/1 00 1010 i i i i sub a, #i a - i a a z, c 1/1 00 1011 i i i i sbc a, #i a - i - c a a z, c 1/1 00 1010 0001 dec a a - 1 a a z, c 1/1 sub a, #1 00 0010 1001 dec b b - 1 b b z, c 1/1 00 0011 1001 dec dp dp - 1 dp u v w c 1/1 00 1000 0001 inc a a + 1 a a z, c 1/1 add a, #1 00 0000 1001 inc b b + 1 b b z, c 1/1 00 0001 1001 inc dp dp + 1 dp u v w c 1/1 logic 00 0100 1010, xxxxxxxxxx anl a, mx a ^ mx a a z 2/2 11 0110 0 i i i anl a, wrx a ^ wrx a a z 1/1 x = 0 7 00 0100 1011 anl a, @m a ^ @m a a u v w z 1/1 00 0101 1010, xxxxxxxxxx orl a, mx a mx a a z 2/2 11 0110 1 i i i orl a, wrx a wrx a a z 1/1 x = 0 7 00 0101 1011 orl a, @m a @m a a u v w z 1/1 00 0110 1010, xxxxxxxxxx xrl a, mx a mx a a z 2/2 11 0111 0 i i i xrl a, wrx a wrx a a z 1/1 x = 0 7 00 0110 1011 xrl a, @m a @m a a u v w z 1/1 00 0111 1010, xxxxxxxxxx cmp a, mx a - mx z, c 2/2 11 0111 1 i i i cmp a, wrx a - wrx z, c 1/1 x = 0 7
w921e840a/W921C840 - 54 - 11. instruction set, continued machine code mnemonic function a b u v w status w/c memo 00 0111 1011 cmp a, @m a - @m u v w z, c 1/1 00 0110 1001 xrl a, b a b a a b z 1/1 00 0111 1001 cmp a, b a - b z, c 1/1 00 1100 i i i i anl a, #i a ^ i a a z 1/1 00 1101 i i i i orl a, #i a i a a z 1/1 00 1110 i i i i xrl a, #i a i a a z 1/1 00 1111 i i i i cmp a, #i a - i z, c 1/1 00 1110 1111 not a not a a a z 1/1 xrl a, #f move 00 0000 0001 mov a, b b a a b z 1/1 00 0000 0010, xxxxxxxxxx mov a, mx mx a a z 2/2 00 0000 0011 mov a, @m @m a a u v w z 1/1 00 0000 0100 mov a, w w a a w z 1/1 00 0000 0101 mov a, v v a a v z 1/1 00 0000 0110 mov a, u u a a u z 1/1 00 0001 0000 mov b, a a b a b ? 1/1 00 0010 0000, xxxxxxxxxx mov mx, a a mx a ? 2/2 00 0011 0000 mov @m, a a @m a u v w ? 1/1 00 0100 0000 mov w, a a w a w ? 1/1 00 0101 0000 mov v, a a v a v ? 1/1 00 0110 0000 mov u, a a u a u ? 1/1 00 0001 0010, xxxxxxxxxx mov b, mx mx b b ? 2/2 00 0001 0011 mov b, @m @m b b u v w ? 1/1 00 0010 0001, xxxxxxxxxx mov mx, b b mx b ? 2/2 00 0011 0001 mov @m,b b @m b u v w ? 1/1 11 0000 i i i i mov a, #i i a a z 1/1 11 0001 i i i i mov b, #i i b b ? 1/1 11 0010 i i i i, xxxxxxxxxx mov mx, #i i mx ? 2/2 11 0011 i i i i mov @m, #i i @m u v w ? 1/1 11 1000 nnnn mov a, wrn wrn a a z 1/1 11 1001 xxxx mov a, px px a a z 1/1 11 1010 nnnn mov b, wrn wrn b b ? 1/1 11 1011 xxxx mov b, px px b b ? 1/1 11 1100 nnnn mov wrn, a a wrn a ? 1/1 11 1101 nnnn mov px, a a px a ? 1/1 11 1110 xxxx mov wrn, b b wrn b ? 1/1
w921e840a/W921C840 publication release date: july 1999 - 55 - revision a3 11. instruction set, conti nued machine code mnemonic function a b u v w status w/c memo 11 1111 xxxx mov px, b b px b ? 1/1 10 0xxx i i i i mov pmx, #i i pmx ? 1/1 mode of port 2 to 6 serial i/o 00 0100 1111 sop ? ? *1 00 0101 1111 sip ? ? *1 rotate or shift 00 0000 1000 srl a an an-1, 0 a3 a z 1/1 n = 3 to 1 00 0001 1000 srh a an an-1, 1 a3 a z 1/1 n = 3 to 1 00 0010 1000 sll a an an+1, 0 a0 a z 1/1 n = 0 to 2 00 0011 1000 slh a an an+1, 1 a0 a z 1/1 n = 0 to 2 00 0100 1000 rrc a an an-1, a0 c, c a3 a z, c 1/1 n = 3 to 1 00 0110 1000 rlc a an an+1, a3 c, c a0 a z, c 1/1 n = 0 to 2 branch 10 1000 0aaa, aaaaaaaaaa jb0 addr addr pc ? 2/2 10 1000 1aaa, aaaaaaaaaa jb1 addr addr pc ? 2/2 10 1001 0aaa, aaaaaaaaaa jb2 addr addr pc ? 2/2 10 1001 1aaa, aaaaaaaaaa jb3 addr addr pc ? 2/2 10 1010 0aaa, aaaaaaaaaa jc addr addr pc ? 2/2 10 1010 1aaa, aaaaaaaaaa jnc addr addr pc ? 2/2 10 1011 0aaa, aaaaaaaaaa jz addr addr pc ? 2/2 10 1011 1aaa, aaaaaaaaaa jnz addr addr pc ? 2/2 10 1100 0aaa, aaaaaaaaaa jmpl addr addr pc ? 2/2 long jump 10 1100 1aaa, aaaaaaaaaa call addr addr pc ? 2/2 10 1101 aaaa callp addr @addr pc a b ? 1/2 indirect address call 10 1110 aaaa tbl addr ? a b z 1/2 look-up table *1: depends on the srmnr, srlnr register
w921e840a/W921C840 - 56 - 11. instruction set, continued machine code mnemonic function a b u v w status w/c memo other 00 0110 1111 rtn stack pc ? 1/3 00 0111 1111 rtni stack pc, z, c z, c 1/3 enint active again 00 0000 0000 nop ? ? 1/1 00 0110 1110 hold ? ? 1/1 00 0111 1110 stop ? ? 1/1 00 0001 11bb clrb @m, bit 0 @m(b) u v w ? 1/1 00 0000 11bb, xxxxxxxxxx clrb mx, bit 0 mx(b) ? 2/2 00 0011 11bb setb @m, bit 1 @m(b) u v w ? 1/1 00 0010 11bb, xxxxxxxxxx setb mx, bit 1 mx(b) ? 2/2 00 0111 1100 clr cf 0 c c 1/1 11 0000 0000 clr a 0 a a z 1/1 mov a, #0 00 0100 1100, 00i i i i i i i i clr evf, #i ? ? 2/2 00 0110 1100 set cf c = 1 c 1/1 00 0100 1110, i i i i i i i i i i mov dp, #i i dp u v w ? 2/2 00 0111 1101 xch u, cu u ? cu u ? 1/1 00 0110 1101 xch v, cv v ? cv v ? 1/1 00 0100 1101 xch a, b a ? b a b z 1/1 notes: dp = {w, v, u} @m = @{w, v, u} @addr = { i, b, a} to be a target address for the callp instruction
w921e840a/W921C840 publication release date: july 1999 - 57 - revision a3 12. package dimensions 40-pin dip 1. dimension d max & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6.general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 b 1 1 e e 1 a 2.055 2.070 52.20 52.58 015 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inch. 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 48-pin qfp e h e y a a seating plane l l 1 see detail f 0.20 0.10 0.008 0.004 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.15 0.090 2.30 0.008 0.008 0.013 0.017 0.20 0.20 0.33 0.40 0.390 0.061 0.098 0.003 0 7 0.394 0.066 0.398 0.072 9.90 0.75 1.55 2.50 10.00 1.70 10.10 1.85 0.398 0.394 0.390 0.600 0.590 0.580 15.25 15.00 14.75 10.10 10.00 9.90 7 0 0.75 0.024 0.036 0.126 0.110 0.60 0.90 2.79 3.20 2.20 0.087 2.10 0.083 0.002 0.05 0.35 0.014 2.00 0.080 0.030 0.580 0.590 0.600 14.75 15.00 15.25 e
w921e840a/W921C840 - 58 - headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792766 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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